1. Field of the Invention
The present invention relates to a sync separator apparatus which, in a display unit having a function of receiving a video signal for a television set, stably separates a sync signal that is required for displaying a video on the display unit from a video signal.
2. Prior Art
As for the conventional methods for separating a sync signal from a video signal, sync separator circuits as that shown in Patent Document 1 have been proposed. In the following, the sync separator circuit that is disclosed in Patent Document 1 is described in reference to FIG. 8.
As shown in FIG. 8, this sync separator circuit has a configuration where a composite video signal 1 is inputted into a first clamp circuit 2 and a second clamp circuit 3 that has been additionally provided. The time constant CR of first clamp circuit 2 is relatively large, making a jitter small at the front edge of sync due to the video level being high or low. Accordingly, a jitter at the front edge of a sync signal 5 that has been separated from this signal by means of a comparator 4 is also small. Meanwhile, the time constant of second clamp circuit 3 is relatively small, making a clamp pulse 7 occur in a slice circuit 6 in a short period of time so that, even in the case where the signal has been switched to a signal having a different average video level, first and second clamp circuits 2 and 3 clamp the signal after being switched in a short period of time. In this manner, a sync separator circuit which has a small change in the front edge due to the video level and a quick response can be put into practice.
Patent Document 1: Japanese Unexamined Patent Publication S57 (1982)-124971
In a sync separator circuit having such a configuration, a configuration, in which a clamp circuit having a large time constant and a clamp circuit having a small time constant are combined, is used, and thereby, the response of sync separation can be made relatively quick even when the average DC voltage of the inputted video signals suddenly changes. However, the number of unstable factors for carrying out sync separation using the above described sync separator circuit increases in the following conditions of use.
Conventional signal sources are signals only of 480i (interlace signal having a number of scanning lines of 480) for the NTSC system and of 576i (interlace signal having a number of scanning lines of 576) for the PAL system in the case of only analog surface wave broadcasting. As a result of the spread of digital television sets in recent years, however, 1080i is used in addition to the above described signals, and 720p (progressive signal having a number of scanning lines of 720) have appeared as a recording medium for cameras. In addition, as a result of the spread of DVD players, 480p and 576p, which have the density twice as high as that of 480i and 576i, have also come into use as video signals.
Accordingly, in television sets in recent years, signals which are inputted into a sync separator circuit are not of a single type, and it becomes necessary for sync separator apparatuses to correspond to various types of video format signals.
In the above described configuration of FIG. 8, however, no sync separation is carried out on video formats where the width of the sync signal, the horizontal frequency rate and the number of scanning lines are different from each other. Furthermore, there are many types in the width of the sync signals for High Definition (hereinafter, referred to as HD) and Standard Definition (hereinafter, referred to as SD) systems, and the width of the sync signal is as narrow as 540 nsec in the format of 720p.
Therefore, in the case where a video signal such as the above described 720p is inputted, the clamp pulse spreads from the conventional clamp period, making it possible that problems may arise where the clamp period overlaps the sync signal period and the video signal period or the clamp period conversely becomes short relative to the width of the sync signal.
In addition, first clamp circuit 2 and second clamp circuit 3 shown in FIG. 8 can receive signals even in the state where there are no clamp pulses, and therefore, a sync tip clamp circuit should be incorporated into the clamp circuit. In addition, it is also shown that the clamp operation can be carried out using a clamp pulse, and therefore, a gate clamp circuit which uses a clamp pulse and carries out a clamp operation according to the timing of the clamp pulse should also be incorporated. Accordingly, first and second clamp circuits 2 and 3, respectively, have the above described two types of clamp circuits incorporated therein, and therefore, the sync separator circuit shown in Patent Document 1 has a configuration where four clamp circuits in total are used.
Furthermore, the period when clamping using a clamp pulse is unclear in the configuration shown in FIG. 8, and therefore, there should be a possibility where a scratch which occurs along with clamping in the gate clamp circuit appears as noise on the display.